For a given node technology, increasing integrated circuit (IC) size typically increases the functionality that can be included on a die. Unfortunately, defects often scale with die area. A large die is more likely to incorporate a defect than is a smaller die. Defects affect yield, and yield loss often increases with increasing die size. Various techniques have been developed to provide large ICs at desirable yield levels.
One approach to providing large ICs is to construct a large IC out of multiple smaller ICs (dice) on a silicon interposer, or to stack IC dice using through-silicon via (TSV) techniques. A silicon interposer is essentially a substrate to which the dice are flip-chip bonded after the silicon interposer has been processed to provide metal wiring and contacts. A silicon interposer typically has several patterned metal layers and intervening insulating layers connected to TSVs. Multiple IC dice are physically and electrically connected to the interposer with micro-bump arrays.
Stacked IC dice use TSV techniques to allow electrical connections to both sides of the parent die. For example, one side (e.g., front side) of a first die (the parent die) is bonded to a printed wiring board, package base, or other substrate, such as with a ball grid array, and the other side (the backside) has a micro-bump or other bonding technique that to which a second, frequently smaller, die is bonded. TSVs extend from the active portion of the first die to the backside of the die, and a microbump array or bonding pads are fabricated on the backside. TSVs are usually made conductive by sputtering a seed layer of metal and then using plating techniques to fill the TSVs with metal, such as copper. However, with sputtering or other conformal deposition techniques, voids can form that lead to incomplete metallization, particularly in conductive TSVs having a length:diameter ratio of 10:1 or greater. Plating process times can also be undesirably long.
Techniques for reliably filling TSVs with a conductive material with reduced manufacturing time are desirable, particularly high-aspect ratio TSVs.